Performance gains of a processor will come from the increase in the number of processor cores per chip, which is evidenced by recent announcements and reflections in the commercial space that multi-core has gone mainstream. A network-on-chip (NoC) for providing communication among the multiple cores enables increasing performance for such a processor.
The main challenge of the NoC design lies in how to meet, in a power efficient way, the bandwidth demand and the stringent latency requirement of a wide range of applications. Many topologies have been proposed for NoC. Most proposed NoCs use a buffered approach where packets are broken into small pieces, called flits (flow control digits). The first flit holds the packet's destination address and sets up the path hop-by-hop for all subsequent flits (belonging to the same packet) to follow. If the head flit is blocked, the entire packet will stop moving and be buffered inside the NoC.
FIG. 1 illustrates a typical buffered node 100 that comprises inputs 103 that include a queue or buffers 102 to buffer data packets received. Each output 105 has an arbitrator or selection logic unit 105 coupled with a multiplexer 106 to decide which input queue 102 will be selected for using the particular output link that the arbitrator is associated with among the plurality of output links.
Since buffers can potentially cause deadlocks, various routing algorithms have been proposed to prevent this from occurring in a buffered NoC. For example, static XY routing algorithm is proposed for 2-dimensional mesh networks, in which packets are routed first along x-direction and then y-direction. This algorithm is deadlock-free, but cannot avoid congestion. In another example, a partially adaptive routing called the turn-model is introduced. In yet another example, the odd-even turn scheme was proposed, which restricts the positions at which turns are allowed to avoid deadlocks. Further, some have introduced adaptive routing into NoCs. Congestion flags are exchanged between neighbor routers. If a router's neighbors are not congested, then it operates on a deterministic mode; otherwise, the adaptive mode is used. In spite of its complexity, this adaptive routing algorithm cannot totally avoid congestion. It only tries to deal with congestions after they are formed, and these routing schemes are operate for buffered networks.
The above discussion shows that conventional buffered NoCs have deficiencies in their approach. For instance, with conventional approaches, to prevent deadlocks, complicated routing algorithms are used adding much to overhead. Furthermore, buffers are expensive in terms of power consumption (both dynamic and static energy), silicon area, and complexity. The above-described background is merely intended to provide an overview of contextual information regarding conventional buffered NoCs, and is not intended to be exhaustive. Additional context may become apparent upon review of one or more of the various non-limiting embodiments of the following detailed description.